AMD or Intel...

[VS Prasad]

What I have read in computer magazines that AMD uses RISC architecture

for their CPUs. You can check the data sheets of AMD.

 

I have run bench marking software, both on Intel and a compatible AMD.

I found that 'MFLOPS' rating of AMD is less than that of Intel. I can provide

the actual values if you want.

 

You can delete my entry if you do not like it. I am willing to accept it.

 

Dr. V. Siva Prasad

Retired Professor of Engineering

Andhra University, India

[Tormod]

The point is that you are wrong when you post a general "AMD uses RISC" statement.

 

Both Intel and AMD produce CISC processors which can translate RISC code, and both have some specialized processors that are RISC based.

[VS Prasad]

While I was in service at our university, I hava seen data sheets

of both Intel and AMD. The salesman told that AMD CPU chip size

is small and runs cool because it uses RISC architecture. I have not

seen the latest brochures. I have understood the line in AMD ads

"performance-per-watt capabilities" that it is still using RISC.

 

If AMD is producing CISC processors for some mini-computer or

server applications, that would not matter the general user.

Largest number of users will be interested about what is available

in the open market.

 

Mr. Tormod, I will be thankful to you if you can give the model

numbers/names of AMD processors that have CISC architecture

which are intended for personal computers.

[Tormod]

Unless I am mistaken, *all* current x86 processors are built using CISC arhitecture, and convert it into RISC code.

 

AMD CPUs use a hybrid CISC/RISC architecture since their 5th generation CPUs (namely K5). Intel started using this approach only from their 6th generation CPUs on. The processor must accept CISC instructions, also known as x86 instructions, since all software available today is written using this kind of instructions. A RISC-only CPU couldn’t be create for the PC because it wouldn’t run software we have available today, like Windows and Office.

 

Inside AMD64 Architecture | Hardware Secrets

 

More sources:

 

Reduced instruction set computer - Wikipedia, the free encyclopedia

Reduced instruction set computer - Wikipedia, the free encyclopedia

[CraigD]

I think some confusion is occurring in this tread due to failure to distinguish external instruction sets from internal ones.

 

Most home computers have CPUs that use the x86-32 or the x86-64 instructions set, which is a “complex instruction set”, meaning many of the instructions (opcodes) it recognizes cause many low-level operations to occur in the CPU. A “pure RISC” CPU strives to have its instruction set correspond in a more one-to-one manner with its low-level operations.

 

Although there are slight variations between different manufacturers’ implementations of these instruction sets. For example, “Intel 64” does not support all of the opcoded that “AMD64” does, though both support the “vendor-neutral” x86-32 standard. Using opcodes unique to a particular manufacturer’s CPU is perilous, however, because such software may not run correctly on a machine with another manufacturer’s CPU, so such extensions are best kept in manageable bit of software, such as hardware firmware and drivers.

 

Internally, a CPU can handle a given opcode however its designer wants. Historically and continuing to the present, Intel has favored implementing as much of the instruction set as possible in actual hardware, while AMD, IBM, HP and others have favored creating a “CPU within a CPU” that has a reduced instruction set. Intel’s strategy is that they’ll get the best performance, because little “translation” between the “external” opcodes it reads from software and the “internal” code used to actually perform them is necessary. AMD and other RISC-focused vendors strategy is that, by making the RISC CPU “inside” the standard CISC CPU much faster (and more energy and thermally efficient), they’ll get better performance despite the need to translate from external CISC opcodes into internal RISC ones.

 

Another advantage of the “RISC CPU inside a CISC CPU” is that the software that translates between the two instruction sets can be made programmable. Such software is called microcode. A CPU built this way can in principle be reprogrammed quickly to function as different external CPUs – for example, be a x86-64 CPU, or a DEC Alpha. Transmeta’s Crusoe and Efficeon CPUs are modern examples of this, though Transmeta calls their microcode “Code Morphing Software”, perhaps to emphasize that it’s more sophiticated than that of 1980s microcode machines such as Data General’s MV series minicomputers, including such features as optimizing itself based on its experience with the sequences of opcodes most used by the computer it finds itself on. Microcode also makes it easier to design and release a CPU, because if a bug is found after release, it can be fixed with a software patch to the microcode.

 

Not all “RISC inside CISC” CPUs use microcode.

 

I business terms, mostly microcode-less RISC inside CISC CPUs, such as AMDs, and mostly pure CISC CPUs, such as Intel’s, have competed fairly evenly against one another, while microcode CPUs, such as Transmeta’s, have not done so well. Transmeta, for example, is down to a 200-employee company with revenues under US$100M/year, with its hopes for future business survival resting as much in the prospect of successfully suing Intel (94,000 employees, $30+B/year revenue) for stealing some of their patented technology as in successfully marketing and improving their products.

[alexander]

since all software available today is written using this kind of instructions

i found that a little hilarious.... when was the last time you have run an application on x86 arch that was written in assembly :D

 

I think it would be more correctly put, if they said most of the compilers today compile the code into CISC instruction set... (although the most widely used one can compile code for just about any architecture, and can be configured to compile code for a specific processor, i am of course talking about GCC)

 

Craig, i don't give rep points often, but you most certainly deserve one :)

 

I can only hope that VS will learn something...

 

P.S. no offense VS, i was really trying to get you to research this... i guess that didn't really work

[TheBigDog]

As I recall the PowerPC chip previously used by Apple was a pure RISC processor. When Apple made the conversion to PowerPC in the mid 90s they abandoned all of their previous software (for the second time). As effective as the chips were, the carpet pulling by Apple in switching to RISC was a big part of eroding their once strong market share.

 

Bill

[alexander]

yes, they are all the way to G5, the main controller in the cell architecture (that is the processor that splits the processing load between cells) is a risc processor (actually they wanted a dual core g5-type chip running at 3GHz originaly, or at least that is the way they described it in the pattent like 4 years ago (they being sony, ibm and toshiba)), sparc (sun) are risc chips, mips (silicon image) are also risc, and so are alpha and their predecessor prism chips.

 

risc chips (mainly mips) are commonly used in video equipment for video processing, as well as satellite equipment (run cooler and require a lot less power) and stuff of that nature.